Welcome to the WEB page of Processor Research Team, RIKEN Center for Computational Science, R-CCS.
To achieve high-performance computing with a supercomputer such as K computer and supercomputer Fugaku, we need to use a huge number of computing nodes in a way that they cooperate with each other using an inter-node network to communicate among them. However, the overall performance may be degraded by the considerable overhead required for global communications and synchronization among the nodes. We are developing computing accelerators to achieve large-scale processing with less performance degradation by introducing a new parallel computing model based on a “Data-Flow” model with localized communication and synchronization. Also, we are developing data-flow accelerators where custom-computing circuits are automatically generated by a high-level synthesis compiler for each target application. Such specially customized hardware structures allow us to achieve high performance processing even for those applications which conventional CPUs are not good at handling. These research results are helping advance usage of the K computer, as well as aiding exploration of new computing models and new architectures for future supercomputers.
- Seeking research scientist or postdoctoral researcher (R-CCS2022:FPGA related).
Dr. Kentaro Sano gave a presentation talk titled “Programming Memory Subsystem Adequately in HLS,” in English at ISC2021 BOF Sessions: Successful FPGA Programming Methods and Tools for HPC, on July 1, 2021 https://app.swapcard.com/event/isc-high-performance-2021-digital/planning/UGxhbm5pbmdfNDQ0NjY3
共著ショートペーパーが国際会議FPGA for HPC Workshop 2021で採録されました/Our Research Short Paper has been accepted for publication in FPGA for HPC Workshop 2021
Author： Takaaki Miyajima and Kentaro Sano, Title： “A memory bandwidth improvement with memory space partitioning for single-precision floating-point FFT on Stratix 10 FPGA” at FPGA for HPC Workshop 2021 held in conjunction with IEEE Cluster 2021. URL：https://sites.google.com/view/hpcfpga2021/submission
Dr. Tomohiro Ueno, Dr. Atsushi Koshiba and Dr. Kentaro Sano gave a presentation talk titled “Virtual Circuit-Switching Network with Flexible Topology for High-Performance FPGA Cluster” at The 32nd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP2021) https://2021.asapconference.org/programOfEvents.html